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STV0502
CCD SENSORS ANALOG PROCESSOR IC
. . . . .
SERIAL BUS CONTROL
VIDEO CORRELATED DOUBLE SAMPLING OF THE CCD SIGNAL DIGITALLY CONTROLLED VARIABLE AMPLIFIER AND BLACK CLAMP LEVEL 8 BITS PIXEL RATE ADC AUDIO MICROPHONE PREAMP WITH SWITCHABLE AGC (RANGE 34dB - 60dB) OR FIXED GAIN
TQFP44 Full (10 x 10 x 1.40mm) (Plastic Quad Flat Pack) ORDER CODE : STV0502
DESCRIPTION The chip integrates the analog functions needed in a CCD Video Camera, more particularly for videoconferencing purpose. The CCD signal is sampled, amplified to a useful level and digitized by an 8 bits ADC. The gain of the amplifier and the black level clamp can be adjusted by a serial bus. PIN CONNECTIONS
BLACK_REF AGC LEVEL TEST ONLY NOT USED OB_CAP
The audio microphone preamplifier allows a microphone to be connected to the chip, which outputs a differential audio line level signal ready for digital conversion or straight amplification. The preamplifier incorporates an AGC to adapt to the income signal level. The AGC is switchable ON/OFF by the serial interface.
GND
GND
VBOT
VTOP
VCC
44 43 42 41 40 39 38 37 36 35 34 VAGCIN CDS_OUT CDS_REF CDS_IN VSS NOT USED NOT USED DATA7 DATA6 DATA5 DATA4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 VBIAS VCC AF_OUTAF_OUT+ CAGC ACC MIC_REF MICRO_IN GND ADC_CLOCK SCLK
DATA3
DATA2
DATA1
DATA0
SDATA_IO
OB
FCDS
VDD
VDD
VSS
FS
VCC
October 1998
1/15
0502-01.EPS
STV0502
PINOUT DESCRIPTION
Pin 1 2 3 4 5 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 42 43 44 6-7 41 Signal VAGCIN CDS_OUT CDS_REF CDS_IN VSS DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] VDD VDD SDATA_IO VSS OB FCDS FS SCLK ADC_CLOCK GND MICRO_IN MICRO-REF ACC CAGC AF_OUT+ AF_OUTVCC VBIAS VCC GND VTOP VBOT TEST ONLY AGCLEVEL OB_CAP BLACK_REF VCC GND NC NC Ana./Dig. Analog Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Type I O I O O O O O O O O I/O I I I I I O O CDS Output CDS Reference CDS Input ADC Data Ground ADC Output - MSB ADC Output ADC Output ADC Output ADC Output ADC Output ADC Output ADC Output - LSB ADC Data Supply Digital Supply Serial Interface Data Wire Digital Ground OB Pulse FCDS Pulse FS Pulse Serial Bus Clock Wire ADC Clock Input Pulse Microphone Ground Microphone Input Microphone Internal Reference Microphone Preamplifier DC Level Capacitor Microphone Preamplifier AGC Capacitor Microphone Preamplifier Output (diff. +) Microphone Preamplifier Output (diff. -) Microphone Preamplifier Supply Microphone Internal Supply (regulated) ADC Supply ADC Ground ADC Top Reference ADC Bottom Reference Test only (AGCOUT/ADCIN) Audio AGC Threshold Configuring Pin Black Clamp DC Loop Capacitor Video Voltage Reference Video Supply Not to be connected Not to be connected
0502-01.TBL
Description Video Variable Gain Input
Video Ground
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STV0502
BLOCK DIAGRAM
VREF
CORRELATED DOUBLE SAMPLING
VIDEO GAIN AMPLIFIER & A/D CONVERTER INTERFACE
6dB/18dB G=1 G=1 G=1
A/D CONV
Range 0-18dB AUDIO INTERFACE
COMP G=1 D/A CONV
BIAS
BIAS
SERIAL BUS INTERFACE
VREG PSRR
AGC
BLACK LEVEL ADJUST & CLAMP
0502-02.EPS
STV0502
FUNCTIONAL DESCRIPTION 1 - Video Section A CCD signal is provided to the STV0502, via a coupling capacitor, as well as the pulses FS/FCDS. The CDS (Correlated Double Sampling) is performing a clamp of the CCD signal during the FCDS pulse. The signal obtained is then sampled during the FS pulse, and held the rest of the period. The resulting signal is then the difference between the useful pixel level, and the pixel level corresponding to no charge which can vary from one pixel to another. Therefore, the parasitic level offset from one pixel to another is removed. This signal is DC coupled to the ACG, amplified by a variable gain amplif ier, bus co ntrolled (0.07dB step), which gain is in the range +6dB to +23.7dB (17.7dB range). Typically, the amplifier is controlled in order to keep the signal at an optimum level (AGC) to be digitized. An extra 12dB can be added up via a bit of the serial interface. In this case the gain range becomes +18dB up to + 36dB. At this point, the signal is clamped to a Black level during the OB pulse. The black level is 5 bits bus controlled, and its range corresponds to [0 LSB ; 31 LSB] of the ADC. The black level is made with a 5 bits DC frequency DAC, using the same VBOTTOM and VTOP voltage references than the ADC for matching purposes. The clamp is made out of a OB pulse sampled comparator between the DAC output voltage (Black) and the ADC input signal. The comparator has a symetrical current output charging a capacitor. The obtained voltage is buffered and used as a feedback to the AGC input stage. This clamp makes sure that ADCin is matched to the DAC black setting during the OB pulse, disregarding any offset in the AGC path. Then the signal is digitized by a fast ADC, clocked at the pixel rate. The output of the chip is then an 8-bit pixel DATA, ready for digital post-processing. 2 - Audio Section The chip integrates a high gain audio amplifier, in order to process low signals coming from a speech microphone, and provide on its output a line level, differential audio signal, for digital conversion, or power amplification. Two modes can be selected : fixed gain mode or AGC mode. In case of AGC mode, a peak detection of the signal is performed in order to regulate the output signal on a defined level of 1.5VPP or 1VPP (non-diff). This regulated level can be chosen at 1.5VPP or 1VPP thanks to a pin at respectively ground or supply voltage (a pullup resistor to supply is already included on chip), for compatibility purposes between the 502 and various back-end chips. The system includes a Low-Noise fixed amplifier (26dB), and a bias circuitry at the front.
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STV0502
FUNCTIONAL DESCRIPTION (continued) It is followed by a Voltage Controlled Amplifier (range 8dB - 34dB), that can be switched into a fixed 26dB gain amplifier. The VCA output is differential and 2 buffers are driving the two output pins, with a load impedance down to 5k. A bias circuitry and an external capacitor (ACC) form a DC feedback loop on the VCA DC bias, in order to correct any DC offset on the VCA output. Finally, a peak detector (double alternance) is used to compare the output signal with the reference Figure 1
Pixel N Pixel N+1 Pixel N+2 Pixel N+3 Pixel N+4 Pixel N+5
threshold, to be regulated at. An external capacitor (CAGC) is used for the AGC time constants. If the signal goes above the threshold, a 500A current is charging the capacitor with a fast reponse time(attack). In case of very big signals, a second charge cureent of about 5mA is given, in order to reduce the period during which the output signal is saturated. Otherwise, a constant 1A current discharges the capacitor with a slow response time (decay). The capacitor voltage controls the VCA gain. This constitues the AGC loop.
CDS_IN t1 FCDS t2 FS t4 t3
CDS_OUT tPROP ADC_IN Sampling Period ADC_CLOCK tDADC DATA_OUT Pixel N-4 Pixel N-3 Pixel N-2 3 CLK Pipe-Line Delay
Notation : - t1 is the delay between the falling edge of FCDS and the beginning of the active pixel level from the CCD. - t2 is the delay between the falling edge of FS and the end of the active pixel level from the CCD.
0502-03.EPS 0502-04.EPS
Pixel N
Pixel N+1
Pixel N+2
Pixel N+3
Pixel N+4
Pixel N-1
Pixel N
Pixel N+1
t1, t2, t3 and t4 must be kept > 0 in the Application.
- tPROP is the propagation delay between CDS_OUT and ADC_IN signals (within the AGC block). - tDADC is the delay on the ADC outputs between the rising edge of the clock and data output.
Figure 2
CDS_IN = CCD Signal Feedtrough Level Signal Level FCDS
FS
CDS_OUT
4/15
STV0502
FUNCTIONAL DESCRIPTION (continued) 3 - Serial Bus Specification It is a 2-wires (data and clock) serial bus, used as a slave. Clock line is monodirectional (input) and allways sent by the master to the chip, whereas Data line is bidirectional (I/O). There are 3 registers (8 bits), both writable/readable. Each register can be addressed by a 4 bits address word, followed by a R/W bit, and an 8 bits word Data (read/write). 2 main patterns can be sent : Reset Pattern and Read/Write pattern. 3.1 -Timings and Protocol The data bit is taken into account when the clock is rising. - Reset Pattern : resets all the registers to their default (Power On) values : format = 16 * (data=1) | 2 * (data=0) (total = 18 clocks) - Read/Write Pattern : format = 4 addr bits | R/W bit | 8 data bits (total = 13 clocks) Figure 3
1 CLK SDATA Minimum 16 CLK Cycles Reset Pattern 2 CLK Cycles
0502-05.EPS
Please note that : 1/ On power On conditions, SDATA line is in Write (Input) Mode. 2/ In case of a read pattern, the SDATA line is automatically set to Read (Output mode) during 8 clock cycles (Data D7 - D0) after R/W bit has been sent, and comes back in Write (Input mode) after the 13th clock cycle. 3/ There is no timing restriction between two consecutive patterns (a pattern being defined as one of the two above). 3.2 - Register Summary
Register Video Amplifier Gain Black Level Adjust Video High Gain Select Test Mode Microphone AGC
X D : unused bits : means useful bits
Address (A3-A0) 0000 0001 0001 0001 0010
Data Format (D7-D0) DDDD.DDDD XXXD.DDDD XXDX.XXXX DDXX.XXXX XXXX.XXXD
Please note that 3 different functions are merged in register address 01.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
Figure 4
1 CLK SDATA A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 10 11 12 13
Read/Write Pattern
5/15
0502-06.EPS
STV0502
FUNCTIONAL DESCRIPTION (continued) 3.3 - Control Data
Video Amplifier Gain Control (8 bits used) Address : 0000 POR value : 0000.0000 ---> 6dB Gain is expressed from CDSoutput to ADC input (ADC range 1.55VPP) - 0.07dB / LSB step - Overall range (256 steps) : 17.7dB
Video Gain (dB) 6 6.07 6.14 ... 7.12 7.19 ... 23.63 23.7 Data 0000.0000 0000.0001 0000.0010 ... 0001.0000 0001.0001 ... 1111.1110 1111.1111
Video High Gain Select (1 bit used) Address : 0001 POR Value : 0 ---> Nominal gain This bit controls an extra 12dB gain in the video path (adding to gain described in previous page).
Video High Gain Select Nominal Gain Extra 12dB Gain Data XX0X.XXXX XX1X.XXXX
Video AGCOUT Test Signal ON/OFF (2 bits used) Address : 0001 POR Value : 00 ---> High Z pad A pin is reserved to output the ADC input signal, or input the ADC input signal for test and evaluation purpose. Those bits control the state of the output buffer. To limit Xtalk and pollutions, the buffer is in High impedance mode during normal operation.
VAGCOUT PIn State Normal Operation (High Z Pin) AGC Output Test ADC Input Test Data 00XX.XXXX 10XX.XXXX 11XX.XXXX
Black Level Adjustment Control (5 bits used) Address : 0001 POR Value : 0001.0000 ---> 16LSB The adjustment is controlling the black reference voltage. However, it is preferred to express the Black level adjustment in terms of the ADC output code variation (in ADC LSBs, compared to the nominal default setting) depending on the Black setting. Typically, 16 LSBs black level is recommended. - 1 ADC LSBs / LSB step - Overall range : 31 ADC LSBs
Black Level (ADC Ouput Variation) 0 LSBs 1 LSBs ... 30 LSBs 31 LSBs Data XXX0.0000 XXX0.0001 ... XXX1.1110 XXX1.1111
Microphone AGC Switch (1 bit used) Address : 0010 POR value : 0000.0000 ---> AGC OFF The switch is controlling the state of the AGC : ON or OFF. In OFF mode, the Micro Preamp. is set at a fixed nominal gain of 52dB. In ON mode, the AGC is operating in a gain range [34dB ; 60dB] (see further in this document for details).
Microphone AGC OFF ON Data 0000.0000 0000.0001
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STV0502
ABSOLUTE MAXIMUM RATINGS
Symbol VDD, VCC VI II Tstg Toper Tlead Parameter Supply Voltage Digital Input Pin Voltage Digital Input Pin Current Storage Temperature Operating Temperature Lead Temperature (10s Max.) Value -0.5, 7 -0.5, VDD + 0.5 1.6 +80 0, +70 +260 Unit V V mA o C o C o C
ESD : The STV0502 withstands 2kV in Human Body Model and 100V in Machine Model for all Pins versus VDD and VSS.
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Max. Value 65 Unit
o
0502-03.TBL 0502-07.EPS 0502-04.TBL
C/W
ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified
Symbol SUPPLY VCC, VDD All Supplies ISUP Total Current Consumption CMOS DIGITAL INPUTS VIL VIH IIL IIH VOL VOH IOL IOH Slevel fCLK DutyC tDR tDW tR tF Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Low Level Output Current High Level Output Current SDATA, SCLK Levels Bus Clock Frequency Clock Duty Cycle Delay between CLK Rising Edge and Data Out Delay between CLK Rising Edge and Data In Clock Rise Time Clock Fall Time 0.3 VDD 0.7 VDD -1.0 1.0 0.4 2.4 4.0 -4.0 CMOS 0.5 50 500 500 V V A A V V mA mA V MHz % ns ns ns ns VCC = VDD = 5V 4.5 40 5 55 5.5 70 V mA Parameter Test Conditions Min. Typ. Max. Unit
CMOS DIGITAL OUTPUTS (4mA drivers)
SERIAL INTERFACE 1 60 700 700 200 200
SCLK Read Mode, see Figure 5 Write Mode, see Figure 5 SCLK SCLK
40 300 300
Figure 5
tR tF
SCLK
tDR
tDW
SDATA_IO
7/15
0502-02.TBL
STV0502
ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified (continued)
Symbol VIDEO CDS RIN CIN INDyn CDS_SR CDS_DR CDS_HM CDS_lin CDS Gain ROUT OUTload FS FCDS PIX_FRE PSRR Input Resistance Input Capacitance Input Dynamic Range S/H Slew Rate S/H Droop Rate S/H Hold Mode Feed through CDS Linearity Overall Input to Output Gain CDS Output Impedance CDS Ouput Load PS Pulse Width FSDS Pulse Width Pixel Rate Power Supply Rejection See timings See timings Pins 4, 21, 22 Measured on Pin 2 (2) Pin 4 Pin 4 Pin 4, before output clipping Pin 2, FS high Pin 2, FS low Pin 2, FS low, fIN = 1MHz Pin 2, 500mVPP (1) Pin 2, normal operation Pin 2, FCDS & FS high 100 12 12 6 12 60 -2 0.6 0.6 -20 -55 0.3 -1 8 11 6 0.7 0.9 +20 -45 1.5 0 250 14 k pF VPP V/15ns mV/s dB % dB ns ns MHz dB Parameter Test Conditions Min. Typ. Max. Unit
VIDEO AMPLIFIER RIN CIN Min. Gain Max. Gain Min. Gain Max. Gain Gset-err Out_Max Input Resistance Input Capacitance Minimum Gain Maximum Gain Minimum Gain Maximum Gain Gain Setting Relative Error Max. Output Signal before clipping Pin 1 Serial bus from H00 to HFF Serial bus = H00/no extra gain Serial bus = HFF/no extra gain Serial bus = H00/extra gain Serial bus = HFF/extra gain Serial bus from H00 to HFF Pin 38, VCC = 4.5V G = 6dB, VIN = 0.8VPP G = 23.7dB, VIN = 0.1VPP Square input Square input Pin 1 to Pin 38 Measured on Pin 38 (2) Measured on Pin 38, compared to Pins 20 and 21 (2) 23.2 35.2 -0.5 1.6 1.6 10 10 15 45 60 15 15 20 2 18 6 23.7 12 35.7 6.5 12.5 0.5 k pF dB dB dB dB dB VPP VPP ns ns ns dB
0502-05.TBL
tR tF tPROP PSRR Xtalk
Output Rise Time Output Fall Time AGC Propagation Time Power Supply Rejection Xtalk from Video to Audio
dB
Notes : 1. Normal operation means FS & FCDS run at specified timings and 12MHz frequency. 2. On a 20Hz to 10MHz frequency range, with 10F filtering capacitors on all supplies, and well splitted supplies and grounds.
8/15
STV0502
ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified (continued)
Symbol 8 BITS ADC & OB CLAMP OB_rise OB_decay BLK_RAN BLK_res BLK_LEV OB High Time Constant OB Low Time Constant Black Level Adjust Range Black Level Adjust Resolution Black Level Adjust Pin 38, OB 0 to 1 Pin 38, OB 1 to 0 Pins 8 to 15, OB high, Serial bus from H00 to H1F Pins 8 to 15, per serial bus LSB step Pins 8 to 15 Bus = H00 Bus = H1F Pin 38 test signal above black clamping level (VBOT) Pin 24 From a sampling to data out CLK positive edge, CLOAD = 20pF Between Pins 36 and 37 Pin 36 Pin 37 Data out, input signal between [VBOT + 25mV ; VTOP - 25mV] 3.2 1.71 3 17 330 3.35 1.8 3.5 1.89 1 31 1 0 31 1.55 12 3 2 33 1.7 4 -2 mV/s mV/ms LSBs LSBs LSBs LSBs VPP MHz CLK cycles ns V %
0502-06.TBL 0502-08.EPS
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
29 1.4
ADC_DN fCLK tPCLK tDADC RLADD VTOP VBOT ADC_lin
ADC Input Dynamic Range (output from 0 to 255) ADC Clock Frequency Output Pipeline Delay (3) Clock to Data Out (4) Ladder Resistance Top Reference Voltage Bottom Reference Voltage ADC Linearity
V
Notes : 3. The signal is being sampled as long as ADC_CLK is high. 4. See Figure 6 for data reading timing constraint.
Figure 6
ADC_IN Sampling Period ADC_CLOCK tDADC DATA_OUT Pixel N-4 Pixel N-3 Pixel N-2 Pixel N-1 Pixel N Pixel N Pixel N+1
Data available on falling edge of clock
Due to tDADC, and to make sure the data are read when they are stable, please read the data on the falling edge of the ADC clock.
9/15
STV0502
ELECTRICAL CHARACTERISTICS Tamb = 25oC, VDD = VCC = 5V, unless otherwise specified (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit MICROPHONE PREAMPLIFIER VBIAS IN_ref RIN GFIX GAGC Bias Audio Voltage Micro Input Voltage Input Impedance Overall Gain Overall Gain Pin 26 Pin 33 Pin 33 AGC Mode off AGC Mode on VAGC = 0.5V VAGC = 4V On Pins 30/31, AGC on, Input = [1.5mVPP ; 30mVPP] AGClevel (Pin 39) = 0 AGClevel (Pin 39) = 5 On Pin 29 when signal out above threshold Step +6dB, CAGC = 2.2F Step -6dB, CAGC = 2.2F Pins 30/31 AGC off : VIN = 5mVPP AGC on : VIN > 40mVPP Pins 30/31 Pins 30/31 Pins 30/31 1VPP out, 1kHz signal, BW 15kHz f = 1kHz, VCC + sine 100mVPP (2) f = 1kHz, VCC + sine 100mVPP (2) CIN = 2.2F, CACC = 10F CIN = 2.2F, CACC = 10F 20 60 -350 1.7 1.7 48 54 3.8 2 50 50 56 20 1.5 1 500 -1 5 2.5 2 2 2.1 0 100 0.15 60 60 250 0.4 350 52 58 34 1.9 1.3 V V k dB dB dB VPP VPP A A ms s VPP VPP V mV % dB dB Hz kHz dB
0502-07.TBL 0502-09.EPS
Regulated Output Level ALC1 ALC2 Ich Idis tATT tDEC AGC Charge Current Output Response Time Output Response Time
1.1 0.7
AGC Discharge Current All the time with AGC on
OUT_Max Output Clipping Level
OUT_DC OUT_OF ROUT THD PSRR CMRR LFc HFc Xtalk
Output DC Voltage Channel DC Mismatch Output Impedance Overall THD PSRR from VCC CMRR from VCC Low Cut-off Frequency High Cut-off Frequency
Xtalk from video to audio Measure on Pins 30/31, compared to Pin 38 (2)
Notes : 2. On a 20Hz to 10MHz frequency range, with 10F filtering capacitors on all supplies, and well splitted supplies and grounds.
Figure 7
INPUT +6dB -6dB
OUTPUT tDEC tATT
10/15
STV0502
I/O DIAGRAMS Figure 8 : VAGCIN Figure 9 : CDS_OUT
1.33kW VAGCIN 1 8.67kW
2
0502-10.EPS
CDS_OUT
0502-11.EPS
Figure 10 : CDS_REF
Figure 11 : CDS_IN
3
CDS_REF
0502-12.EPS
CDS_IN
4
0502-13.EPS
10kW
Figure 12 : DATA[7:0]
Figure 13 : SDATA_IO
DATA[7:0] Pins 8 to 15
0502-14.EPS
SDATA_IO 18 220W
0502-15.EPS
Figure 14 : OB, FCDS, FS, SCLK, ADC_CLOCK
Figure 15 : MICRO_IN
OB, FCDS, FS SCLK, ADC_CLOCK Pins 20, 21, 22, 23, 24
220W
MICRO_IN 26
0502-16.EPS 0502-17.EPS
11/15
STV0502
I/O DIAGRAMS (continued) Figure 16 : MIC_REF Figure 17 : ACC
27 MIC_REF
28 ACC
0502-18.EPS
Figure 18 : CAGC
Figure 19 : AF_OUT+, AF_OUT-
29 CAGC
10kW
AF_OUT+, AF_OUTPins 30/31
0502-21.EPS
10kW
0502-20.EPS
Figure 20 : VBIAS
Figure 21 : VTOP
33 VBIAS
0502-22.EPS
36 VTOP
0502-23.EPS 0502-25.EPS
22kW
10kW
330W
Figure 22 : VBOT
Figure 23 : VAGCOUT
40kW
330W
10kW 37 VBOT
38 VAGCOUT
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0502-24.EPS
0502-19.EPS
STV0502
I/O DIAGRAMS (continued) Figure 24 : AGCLEVEL Figure 25 : OB_CAP
AGCLEVEL 39
0502-26.EPS
40 OB_CAP
0502-27.EPS
Figure 26 : BLACK_REF
42 BLACK_REF
0502-28.EPS
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STV0502
TYPICAL APPLICATION
VCC Video 10m F 1m F 220nF 1m F 1m F VDD ADC 10m F
44
GND
43
VCC
42
BLACK_REF
41
NC
40
OB_CAP
39
AGCLEVEL
38
TESTONLY
37
VBOT
36
VTOP
35
GND
34
VCC
10m F VBIAS 33 VCC 32 AF_OUT- 31 LINE OUTPUTS VCC Micro 10m F
1 VAGCIN 2 CDS_OUT
1m F
3 CDS_REF
From CCD
4 CDS_IN
33nF
AF_OUT+ 30 6.8m F
5 GND 6 NC 7 NC 8 DATA[7] 9 DATA[6]
DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]
CAGC 29
3.3kW 10m F
STV0502
ACC 28
10m F
MICRO_REF 27 5.1kW MICRO_IN 26 2.2m F GND 25
3 x 1N4148 1kW
MICROPHONE
10 DATA[5]
SDATA_IO
ADC_CLOCK 24
ADC_CLOCK
11 DATA[4]
DATA[3] DATA[2] DATA[1] DATA[0] VDD VDD
SCLK 23
FCDS
GND
OB
FS
SCLK
12
13
14
15
16
17
18
19
20
21
22
SERIAL SDATA INTERFACE
0502-29.EPS
VDD OB FCDS FS
14/15
STV0502
PACKAGE MECHANICAL DATA 44 PINS - FULL PLASTIC QUAD FLAT PACK (THIN) (TQFP)
A A2 44 e A1 34 0,10 mm .004 inch SEATING PLANE
B
1
33
11
23
E3 E1 E
12
D3 D1 D
22
c
L1
L
K
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 L L1 K
Min. 0.05 1.35 0.30 0.09
Millimeters Typ.
1.40 0.37 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00
Max. 1.60 0.15 1.45 0.40 0.20
Min. 0.002 0.053 0.012 0.004
Inches Typ.
0.055 0.015 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039
Max. 0.063 0.006 0.057 0.016 0.008
0.45
0.75
0.018
0.030
4Y.TBL
0o (Min.), 7o (Max.)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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PM-4Y.EPS
0,25 mm .010 inch GAGE PLANE

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